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? integrated circuits group id 24 6 se rie s fla sh m emo ry car d (model n umb ers : id 24 6 xx x ) spec no.: c ps 00 0 8 e - 00 1 p r oduc t over v ie w
shari= id246 series product overview l handle this document carefully for it contains material protected by international copyright law. any repro- duction, full or in part, of this material is prohibited without the express written permission of the company. l when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2). even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). * office electronics . instrumentation and me.asuring equipment * machine tools * audiovisual equipment . home appliances * communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibil- ity for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * control and safety devices for airplanes, trams, automobiles, and other transportation equipment . mainframe computers - traffic control systems * gas leak detectors and automatic cutoff devices * rescue and security equipment . other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * aerospace equipment . communications equipment for trunk lines . control equipment for the nuclear power industry * medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. l please direct all queries regarding the products covered herein to a sales representative of the company. cps0008e-00
sharp id246 series product overview 2 1. 2. 3. 4. 5. 6. 7. 8. 9. contents intnxluction ................................................................................................................. p. features ....................................................................................................................... p. block diagram ............................................................................................................ p. pin connections .......................................................................................................... p. signal description ...................................................................................................... p. functions ..................................................................................................................... p. 6. 1 common memory.. ......................................................................................... p. 6. 2 attribute memory ................ ........................................................................... p. 6. 3 function table ..... . .......................................................................................... p. card information structure (cis) ............................................................................... p. card control ............................................................................................................... p. 8. 1 reset ............................................................................................................. p. 8. 2 status register ................................................................................................ p. 8. 3 write protect switch ....................................................................................... p. 8. 4 identifier codes. .............................................................................................. p. component management register (cmr) ................................................................. p. 10. commad definitions.. ............................................................................................... p. 10. 1 query command.. p. ....... .................................................................................... lo. 2 sts configuration command ........................................................................ p. 11. electrical specifications ............................................................................................. p. 11. 1 absolute maximum ratings ........................................................................... p. 11. 2 recommended operating conditions. ............................................................ p. 11. 3 capacitance ..................................................................................................... p. 11. 4 ac input/output test conditions .................................................................. p. 12. dc characteristics ...................................................................................................... p. 13. ac characteristics ...................................................................................................... p. 13. 1 common memory read operations ............................................................... p. 13. 2 command write operations : common memory .......................................... p. 13. 3 attribute memory read operations ............................................................... p. 13. 4 attribute memory write operations .............................................................. p. 13. 5 power-up/power down.. ................................................................................ p. 14. specification changes ................................................................................................ p. 15. other precautions.. ...................................................................................................... p. 16. external diagrams ...................................................................................................... p. 3 3 4 5 6 7 7 8 9 9 12 12 12 12 12 15 17 18 21 22 22 22 22 22 23 25 25 27 33 34 35 36 36 37
sharp id246 serifs product overview 1. introduction this datasheet is for sharp?s id246 series flash memory card. this datasheet provides all ac and dc character- istics (including timing waveforms) and a convenient reference for the device command set and the cards inte- grated registers(including the flash memory?s status registers). this datasheet provides description of the meth- ods which are very helpful for customer to use the card. 2. features 2.1 type 2.2 overview 2.3 interface flash memory card common byte memory capacity word device attribute memory capasity supply voltage id246pxx id246rxx id246sxx 32mbyte 40mbyte 48mbyte 16mword 20mword 24mword lh28f032skd lh28f032skd lh28f032skd 8devices lodevices 12devices 2kbyte (note:standard cis is not writable) vcc=sv ! vpp=sv, vcc=3.3v i vpp=3.3v,5v access time erase unit program/erase cycles external dimensions 150ns(@vcc=%) 250ns(@vcc=3.3v) 64k word blocks 1 oo,ooocycles/block pcmcia type 1 54.0x 85.6x 3.3mm parallel i/o interface 2.4 function table see function table in page. 9 2.5 pin connections see pin connections in page. 5 2.6 type of connector conforms to pcmcia pc card standard 95 card use connector card connector: jc20-j68s-nb3 by jae or fcn-568j068-g/o by fujitsu or icm-c68s-ts 13-5035a by jst 2.1 operating temperature 0 to 60c 2.8 storage temperature -20 to 65c 2.9 not designed for rated radiation hardened.
sharp id246 series product overvlew 3. block diagram control logic zvcc vppl . vpp2 ~ : : : i i i i : : . m ? ? - - - - - - - - vpp2 vcc vpp 1 vcc t t flash memory flash memory 3 data wp#k+ -bwp# data *? . e add ce#l* + cm add 4 -rp# a we# 4---, *wi3 rpwj sts oe# m - oe# sts - /a vpp2 t /i vcc vpp2 vcc flash memory b data wfj# 4--- b add ce# 4--- ** we# 4---(c - sts oe# 4i()-- flash memory l w data * - - + ce# add + - - l we# rp#-+ * oe# sts ---( ? figure 1. block diagram
sharp id246 series product overview 5 4. pin connections table 1. pin connections t i i ;r signal i/o i i function active 4 i i ;,? signal i/o i i function active low low high low low t1003-01 i i 40 ~d,j 39 dig i i i 1 i/o idata bit 14 1 i/o idata bit 13 5 d6 6 d7 i/o data bit 6 i/o data bit 7 41 dig 42 cez# i/o data bit 15 i card enable 2 7 cei# 8 aio i card enable 1 i address bit 10 43 vsi# 44 rfu 0 voltage sense 1 reserved 9 oe# 10 al1 i output enable i address bit 11 1 11 1as i i iaddress bit9 i i 45 imu 1 ireserved i 1 1 15 iwe# i i i write enable i i i i 1 address bit 20 i 16 irdytssy# i o iready busy low 1 1 50 iax i i iaddress bit 21 17 vcc 18 vppi supply voltage program voltage 1 22 ia7 i i iaddress bit7 1 1 56 ia25 i 1 (address bit 25 1 1 57 ivs2# i 0 ivoltage sense 2 23 as 24 as i address bit 6 i address bit 5 1 1 58 ikeset i i (reset 25 a4 26 as i address bit 4 i [address bit 3 -ii 62 63 (bvd2 ibvd~ i 0 0 battery battery voltage voltage detect detect 2 1 i 30 (do i i/o (data bit 0 1 i/o (data bit 8 1 34 (gnd i 1 ground 1 1 68 (gnd i (ground i cpsoq08e.001
sharp id246 series product overview 6 1 5. signal description table 2. signal description function address inputs: 40425 these are address bus lines which enable direct addressing of memory on the card. signal ao is not used in word access mode. data input/output do through dig constitute the bi-directional data bus. drs is the most significant bit. ,,. pull-down i (250kn @vcc=sv) h-d15 card enable 1 & 2: cei# enables d+d7, ce2# enables da-dig. :ei#,cez# >e# output enable: active low signal gating read data from the memory card. write enable: active low signal gating write data to the memory card. ready/busy outpup ne# indicates status of internally timed erase or write activities. id246 series has two types of ready/busy output mode; pcmcia mode and high-performance mode. in pcmcia mode, a high output indicates the memory card is ready to accept accesses. a low output indicates that a device in the memory card is busy. in high-performance mode, the card outputs low when the card is in default state. a high output indicates at least one of flash memory devices in the card comes to be ready to accept accesses. card detect 1 & 2: 0 idylbsy# :di#, cdz# these signals provide for card insertion detection. the signals are connected to ground internally on the memory card, and will be forced low whenever a card is placed in the socket. the host socket interface circuitry shall supply 10k or larger pull-up resistors on these signal pins. write protect: 0 pull-down of2 t o low:puil-down on high:pull-up 1ookn write protect reflects the status of the write protect switch on the memory card. wp set to high = write protected. i vp write / erase power supply 1 & 2: i (ppi .vpp2 [cc card power supply: i ind ground: i eg# register select: provides access to attribute memory when reg# is low. reset active high signal for placing card in power-on default state. battery voltage detect 1 & 2: these signals are pulled high to maintain sram card compatibility. voltage sense 1 & 2: eset ;vdi, bvdz 0 pull-up 1ookq i notifies the host socket of the cis?s vcc requirements.vs~# is pulled- lawn to ground when using the standard cis, that indicate 3.3v operating is available. reserved for future use t1172e.01 o vsi#: pull-down i vs2#: n.c. 'sl#, vs2# cps0008e40'
shari= id246 series product overview 7 6. functions 6.1 common memory 6. 1. 1 common memory architecture figure 2 shows common memory architecture of id246 series flash memory card. device pair is consisted of two pieces of flash memory devices. each device has individually erasable and lockable blocks. all blocks are divided into odd bytes and even bytes. each device pair and block is selected by address bits. table 3 shows definitions of address bits. device pair 5 devll 1 devio = = = devici pair 2 devs 1 dev4 deviti pair 1 dev3 1 dev2 i device pair 0 lh28fo32skd lh28fo32skd - jgx-8&- - - -4;i z 8jjii - devl devo / / bank1 bank0 /? blodc63 / / 1 i ?w ?i i / i i ?i i i 1 bank1 1 bank0 odd even word mode yte mode i\1 word mode odd-byte mode byte mode d15-d8 d7-do f1076e4)? figure 2. common memory architecture table 3. address difinitions address pifinitions 32mb ,4omb ,48mb select even / odd byte in the byte access a0 mode. select address in the block. a16-al (64kj3/block) select a block. a21 -a17 (32blocks/bank) select a bank a22 (2banks/device) select a device pair. a25 -a23 t1173e-01
shari= id246 series product overview 8 6. 1.2 erase erase is executed one block at a time. erasable block size is 64k bytes in byte access mode and 128k bytes in word access mode. 6. 1.3 address decoding the higher address area of id246 series flash memory card which goes beyond common memory area is not decoded in common memory access. it means that the system will access to random memory address of the memory card even if system will try to access to the memory address which exceeds memory capacity of the card. please do not access to the memory address which goes beyond memory capacity of the card. as an enhanced function, the memory card enables to output invalid data (either of ooooh or ffffh) when system will access to the memory address which exceeds memory capacity of the card. please contact our sales & market- ing support to find concrete way of setting. 6.2 attribute memory figure 3 shows attribute memory map of id246 series flash memory card. attribute memory is contained within the card control logic. attribute memory contains the card information structure (cis) and component man- agement registers (cmrs). the cis contains tuple information and is located at even byte addresses beginning with address ooooh (please refer to section 7). the standard cis of id246 series flash memory card is hardwired and is for read only. as an enhanced function, the hardwired cis area is switchable to eeprom so that customer can program required cis. please contact our sales & marketing support to find concrete way of setting. the cmrs are located at even byte addresses beginning with address 4000h (please refer to section 9). address ,-?--? t--?-?, odd even f1003-01 figure 3. attribute memory map
sharp id246 series product overvibw 6.3 function table 6.3.1 common memory access table 4. common memory mode stand-by byte read word read odd byte read byte write word write odd byte write tcess h h l h h l don?t care odd h l l x h l odd even h l h x h l odd don?t care 6.3.2 attribute memory access table 5. attribute memory access mode reg# ce,# ce,# a, oe# we# d,,, d 7-o stand-by x h h x x x high-z high-z l h l l l h even byte read high-z l h l h l h high-z xx word read l l l x l h xx even odd byte read byte write word write odd byte write l l h x l h xx high-z l h l l h l don?t care even l h l h h l don?t care don?t care l l l x h l don?t care even l l h x h l don?t care don?t care ts1059e-02 xx:output data is invalid. the standard cis is for read only. write operation is only for cmrs and cis on eeprom 7. card information structure (cis) the cis is contained within attribute memory (please refer to section 6.2). table 6 shows standard cis tuples, but it is for read only. as an enhanced function, the hardwired cis area is switchable to eeprom so that customer can program required cis. please contact our sales & marketing support to find concrete way of setting.
sharp id246 series product overview table 6. standard cis address 1 value 1 description i 1 address 1 value 1 ooh 1 olh , 02h / 04h -1 1 46h 1 53h isproduct info i 48h 4ah 48h h 41h a rash memory i access time 150ns 4ch 52h r 4eh 50h p i i 08h 7eh 9eh capacity 32mb 40mb 50h 52h 54h 56h ooh end text 4yh i 4th d 32h 2 58h 34h 4 5ah 53h s 5ch 52h r 5eh 20h space 10h 12h 02h conditions 3vcc 57h flash memory 48h h 41h a 52h r 6ah 1 50h ip 6ch 1 20h ispace 60h 62h 64h 66h 6xh ooh endtext 53h s :maker info access time 250ns capacity 32mb 40mb 48mb end of tuple i i 1ch 04h tuple link i 43h c 4i=h 0 72h 1 52h ir 74h i 50h ip 6eh 70h 1eh ( 1ph irom i access time 200ns capacity 2kb 76h 1 4fh 0 78h i 52h ir end of tuule 7ah ( 41h a 7ch 1 54h it 28h 05h tuple link 2ah 1 02h iconditions 3vcc rom 1 2cb 1 1ph 7eh 80h 82h 84h 86h 88h 8ah 49h i 4i=h 0 4eh n ooh end text pfh end of tuple 1 ah configuration info 05h tuple link 2eh 30h 32h 34h 36h 38h 3ah 2ab access time 2oor-r~ olh capacity 2kb pi% end of tuple 18h jedec code id 02h tuple link boh manufacture code doh device code last index of configuration table 3ch ooh end of tuple 3eh 15h version info level 1 40h 23h tuple link 42h 04h major version 44h olh minor version cps0008e401
sharp id246 series product overview table 8. standard cis (continued) address 1 value 1 description i 9ah 08h tiple link 9ch olh index 9eh 02h vcc & vpp aoh a2h a4h 79h parameter selection 55h vcc voltage 5v och icc static a6h a8h 06h icc average 06h icc peak aah 23h icc powerdown ach 1 1bh 1 contieuration table entrv 2 i aeh boh 09h tuple link 02h index b2h b4h olh vcc onry 79h parameter selection b6h b8h b5h vcc voltage 5v 1eh bah bch beh och icc static 7dh icc average 7dh icc peark coh 1 1bh (icc powerdown i c2h c4h 1eh device geometry 06h tuple link c6h 1 02h bus c8h 1 llh ierase cah ) olh iread size i cch ceh olh write size olh partation: lblock doh d2h 0 1 h non-interleaved 20h manufacturer id d4h 1 04h itunle link i -+e-ta manufacturer code deh eoh 2 1 h function identification 02h tuple link e2h e4h 0 1 h function: memory ooh system: none e6h ffh end of cis i cps0008e-00
sharp id246 series product overview 12 8. card control 8. 1 reset the card is in initial state directly after power-up. but we recommend to do reset operation after power-up to make sure to initialize the card. during block erase, byte write, or lock-bit configuration modes, an active reset will abort the operation. rdyi bsy# remains low until the reset operation completes. memory contents being altered are no longer valid; the data may be partially erased or written. the host must wait after reset goes to logic-low (vil) before it can write another command, as determined by tpt.nvl. it is important to assert reset to the card during a system reset. if a cpu reset occurs without a card reset, the host will not be able to read from the card if that card is in a different mode when the system reset occurs. for example, if an end-user initiates a host reset when the card is in read status register mode, the host will attempt to read code from the card, but will actually read status register data. sharp?s id246 series flash memory card allows proper card reset following a system reset through the use of the reset input. 8. 2 status register each flash memory device in the card has status register. the status register may be read to determine when a write, block erase, or lock-bits configuration is complete, and whether that operation completed successfully (please refer to table 7). it may be read at any time by writing the read status register command (70h, 7070h) into the cui. in word access mode, the status register data of even byte devices are output to d7-0,and the status register data of odd byte devices are output to d15-8. 8. 3 write protect switch the id246 series flash memory card has a write protect switch on the back of the card. when the switch is in the write protect position, the card blocks all writes to the common and attribute memory without card management registers region (see figure 4 ). 8.4 read identifier codes / block status code manufacture code and device code are contained within each flash memory device in the memory card. the identifier code operation is initiated by writing the read identifier codes command (90h, 9090h) into the cui of each memory device. the specific address of each device is necessary to be selected to read these codes (table 9). writeble position r i write pro=sition note: the write protect switch is shown by the black square. figure 4. write protect switch cpso@xei)ol
sharp id246 series product overview 13 table 7(a). status register definition wsms 7 bess 1 ecblbs 1 wsblbs vpps wss dps r 6 5 4 3 2 1 0 notes: sr.7 = write state machine status 1 = ready check ry/by# pin or sr.7 to determine block erase, full 0 = busy chip erase, (multi) word/byte write or block lock-bit configuration completion. sr.6 = block erase suspend status sr.6-0 are invalid while sr.7=?0? 1 = block erase suspended 0 = block erase in progress/completed if both sr.5 and sr.4 are ?1?safter a block erase. full chip erase,(multi) word/bite write, block lock-bit configuration or sr.5 = erase and clear block lock-bits sts configuration attempt, an improper command sequence status was entered. 1 = error in erase or clear block lock-bits 0 = successful erase or clear block lock-bit sr.3 does not provide a continuous indication of vpp level. the wsm interrogates and indicates the vpp level only 5r.4 = write and set block lock-bit status after block erase, full chip erase, (multi) word/byte write or 1 = error in write or set block lock-bit block lock-bit configuration command sequences. sr.3 is 0 = successful write or set block lock-bit not guaranteed to reports accurate feedback only when vppi=vppn 1. sr.3 = vp? status 1 = vpp low detect, operation abort sr. 1 does not provide a continuous indication of block 0 = vpp ok lock-bit values. the wsm interrogates block lock-bit, and wp# only after block erase, full chip erase, (multi) 3r.2 = write suspend status word/byte write or block lock-bit configuration command 1 = write suspended sequences. itinforms the system, depending on the 0 = write in progress/completed attempted operation, if the block lock-bit is set and/or wp# is not vih. reading the block lock configuration codes after jr. 1 = device protect status writing the read identifier codes command indicates block 1 = block lock-bit and/or wp# lock detected, lock-bit status. operation abort 0 = unlock sr.0 is reserved for future use and should be masked out when polling the status register. 3r.0 = reserved for futurjz enhancements tllfnc~n, 7 6 5 4 3 2 1 0 notes: xsr.7 = state hlachine status 1 = multi word/byte write available 0 = multi word/byte write not available xsr.qo=reserved for future enhancements after issue a multi word/byte write command: xsr.7 indicates that a next multi word/byte write command is available. xsr.b-0 is reserved for future use and should be masked out when oolline the extended status register.
sharp id246 series product overview 14 table 8. identifier codes / block status select device-pair address in device even/odd data output d,-d, k%1 hia, a0 32mb ,4omb, 48mb manufacture identifier oooooh 0:even code dpa ocoolh 1:odd boh device identifier code dpa 00002h 00003h 0:even 1 :odd doh block status code block status code dpa xooo4h xooo5h (x: select block) d,: o=unlocked, l=locked d,: o=last erase operation 0:even completed successfully 1:odd l=last erase operation did not completed successfully d,-d,: reserved note: a,, is ignored in word access mode, and d,5-d, outputs the odd byte data. dpa: address as select device pair blkd: block lock configuration data mlkd: master lock configuration data tl 1meol
sharp id246 series product overview 9. component management registers (cmr) component management registers (cmr) are mapped at even byte locations beginning at address 4000h in attribute memory. 9. 1 9. 2 9. 3 9. 4 configuration option register (address:4000h) address bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 4000h sreset reserved sreset: l=reset state o=end reset cycle card configuration register (address:4002h) address bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 4002h reserved pwdn reserved pwdn: l=power-down device pairs that apointed by sleep control register(4118h-411 ah) are in power- down. o=power-up socket and copy register (address:4006h) address bit.7 bit.6 bit.5 4006h reserved copy no. soket no.: socket number copy no.: copy number bit.4 bit.3 bit.2 bit.1 soket no. bit.0 i the card may use to distinguish between similar cards installed in a system. tlol-01 card status register (address:41 ooh) address bit7 bit.6 bit.5 bit.4 bit.3 bit.2 bit.1 bit.0 4100h adm ads sreset cmwp pwdn ciswp wp rdyibsy adm: ored value of the ready/busy mask register. 1 = any device is masked. 0 = all devices are not masked. ads: ored value of the sleep control register. 1 = any device-pair is controled power-down by bit.2 of the card configuration register. sreset: reflects the bit.7 of the configuration option register. cmwp: reflects the bit.1 of the write protection register. pwdn: reflects the bit.2 of the card configuration register. ciswp: reflects the bit.0 of the write protection register. wp: indicates the write protect switch status. 1 = write protect switch: on 1 = write protect switch: off rdy/bsy: reflects the ready/busy status register. 1 = all devices are ready. 0 = any device is busy. tio54-01
sharp id246 series product overview 16 9. 5 write protection register (address:41 04h) address 4104h bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 reserved blken cmwp blken: block locking enable 1 = enable block locking 0 = all block unlocked common memory write protect bit.0 ciswp cmwp: 1 = common memory without cis region in write protect status common memory cis write protect ciswp: 1 = common memory cis in write protect status ti 176e4l 9. 6 sleep control register (address:41 18h-411 ah) address bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 411al-l reserved 4118h reserved dev 10/l 1 dev8/9 dev6/7 dev4/5 dev2j3 devo/l l= select sleep mode device-pair if set to ?i?, the corresponding device-pairs are putted into deep powerdown mode by pwdn bit of configuration status register. tiw741 9. 7 ready/busy mask register (address:41 20h-4122h) address bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit.1 bit.0 4122h reserved devll devlo dev9 dev8 4120h dev7 dev6 devs 1 dev4 dev3 dev2 devl devo 1 =mask the rdy/bsy# the corresponding device?s rdy/bsy# signals to set bit are ignored for cards rdy/bsy# output. 9. 8 ready/busy status register (address:41 30h-4132h) address 413231 4130h bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit. 1 bit.0 reserved devi 1 devio dev9 dev8 dev7 dev6 devs dev4 dev3 dev2 devl devo l=ready o=busy each bit indicates the corresponding device?s rdy/bsy# signal. tloilol 9.9 ready/busy mode register (address:41 40h) address bit.7 bit.6 bit.5 bit.4 bit.3 bit.2 bit.1 bit.0 4140h reserved rack mode rack: ready acknowledge bit must clear this bit after receiving ready status to prepare for next device?s ready transition. mode: rdy/bsy# mode 1 = high-performance mode 0 = pcmcia mode timsol
sharp id246 series product overview 10. command definitions device operations are determined by writing specific commands to the command user interface. table 9 defines the commands. table 9. command definitions read identifier codes word/byte write level-mode for erase and write (ry/by# mode) sts configuration pulse-mode for erase write da b8h (bsbsh) write da olh (ololh) sts configuration b8h 02h pulse-mode for write write da (bsbsh) write da (0202h) sts configuration write da b8h write da 03h pulse-mode for erase and write (bsbsh) (0303h) t115oe-m address data ia =identifier cede address id =identiiier codes wa =write address wd =write data ba =block address srd =data from status register da =device address qa =quety offset address qd =data read from query database note: 1. following the read identifier codes command, read operations access manufacture, device, block status codes. 2. status register may be read to determine when a write, block erase, or lock bit configuration is complete, and whether that operation completed successfully. 3. if the block is locked, block erase or write operations are desabled. 4. following the third bus cycle,inputs the write address and write data of ?n?+l times.finally, input the confirm command ?doh?. cp%008e40
sharp id246 series product overview 10.1 query command query database can be read by writing query comman d (98h). following the command write, read cycle from address shown in table 1 l-15 retrievethe critical information to write, erase and otherwise control the flash component. in word mode, ds-dis output the query data of odd byte devices. table 10. example of query structure output a,, a,, a,, a,, a,, a, 1 , 0 , 0 , 0 , 0 , 0 (20h) x8 mode 1 , 0 , 0 , 0 , 0 , l(21h) 1 ,o,o,o, 1 ,ogw 1,0,0,0,1,1(23h) a,, a,, a,, a,, a, xl6 mode l,o,o,o,o (10h) 1 ,o,o,o,l (11h) offset address (a6 - al) a0 0 = even 1 = odd x t output i %-d* high-z high-z high-z high-z ?q? ?r? d,-do ?q? ?q? ?r? ?r? ?q? ?r? tllsze-01 10. 1. 1 block status register this field provides lock configuration and erase status for the specified block. these informations are only avail- able when device is ready (sr.7=1). if block erase or full chip erase operation is finished irregulary, block erase status bit will be set to ?l?,this block is invalid. table 11. query block status register offset (word address) length description (b a+2)h olh block status register do : block lock configuration o=block is unlocked l=block is locked dl : block erase status o=last erase operation completed successfully l=last erase operation not completed successfully d2-7: reserved for future use note: l.ba=the beginning of a block address. t1153e41
shari= id246 series product overview 19 l 10. 1.2 cfi query identification string the identification string provides verification that the component supports the common flash interface specifi- cation. additionally, if indicates which version of the spec and which vendor-specified command set(s) istare) supported. table 12. cr query identification string offset (word address) length description loh.1 lhj2h 03h query unique ascii string ?qry? 5 lh,52h,59h 13h,14h 02h primary vendor command set and control interfase id code olh,ooh (scs id code) 15hj6h 02h addressfor primary algorithm extended query table 3 lh,ooh (scs extended query table offset) 17hj8h 02h alternate vendor command set and control interfase id code ooooh (ooooh means that no alternate exists) i9hjah 02h address for alternate algorithm extended query table ooooh (ooooh means that no alternate exists) t1154e-01 10. 1. 3 system interface information the following device information can be useful in optimizing system interface software. table 13. system information string offset (word address) ibh length olh description v,, logic supply minimum write/erase voltage 27h (2.7v) lch . i i olh v, logic supply maximum write/erase voltage 55h (5.5v) idh leh fh !oh !lh !2h !3h !4h !5h :6h olh olh olh olh olh olh olh oih oih olh v, programming supply minimum write/erase voltage 27i.i (2.7v) v, programming supply maximum write/erase voltage 55h (5.5v) typical timeout per single byte/word write 03h (23=8 usec) typical timeout for maximum size buffer write (32 bytes) 03h (2%4 usec) typical timeout per individual block erase oah (oah=lo , 2i?=1024 msec) typical timeout for full chip erase ofh (ofh=15 , 2ij=32768 msec) maximum timeout per single byte/word write, 2n times of typical 04h (r=16 , 8 usec x16=128 usec) maximum timeout maximum size buffer write, 2n times of typical 04h (24=16, 64 usec x16=1024 usec) maximum timeout per individual block erase, 2n times of typid 04h (2?=16, 1024 msec x16=16384 msec) maximum timeout for full chip erase, 2n times of typical 04h (24=16, 32768 msec x16=524288 msec) t1155e.01
sharp id246 series product overview 20 10. 1. 4 device geometry definition this field provides critical details of the flash device geometry. table 14. device geometry definition offsel (word address) length i description 2lh olh 28h. 29h 02h 2ali. 2bh 02h 2ch olh 2dh, 2eh 02h 2fh. 30h 02h device size 15h (15h=21,22?=2097152=2m bytes flash device interface description 02h,ooh (x8/x16 supports x8 and xl6 via byle#) maximum number of bytes in multi word/byte write 05h.ooh (2?=32 bytes) number of erase block regions within device 01 h (symmetricatly blocked) tbe number of erase blocks lfh,ooh (lfh=31 =>31+1=32 blocks the number of ?256 bytes? cluster in a erase block 00h,olh (olooh=256 =>256 bytes x 256=643 bytes in a erase block) t1?5641 10. 1. 5 scs oem specific extended query table certain flash features and commands may be optional in a vendor-specific algorithm specification. the optional vendor-specific query table(s) may be used to specify this and other types of information. these structures are defined solely by the flash vendor(s). table 15. scs oem specific extended query table offset (word address) 3lh,32h,33h length 03h pri 50h, 52h, 49h description 34h 35h 36h. 37h. 38h. 39h olh olh 04h 3 1 h (1) major version number , ascii 30h (0) minor version number, ascii ofh, ooh, ooh, coh optional command support bito=l : chip erase supported bitl=l : suspend erase supported b&2=1 : suspend write supported bit3=1 : lock/unlock sqported bit4=0 : queued erase. not supported bit5-31=0 : reserved for future use. 3ah oih olh supported functions after suspend bito=l : write supported after erase suspend bit l-7=0 : reserved for future use 3bh, 3ch 02h 03h, ooh block status register mask bitor : block status register lock bit (bsr.01 active bitl=l : block status register valid bit [bsr.l] active biq-15=0 : reserved for future use 3dh olh 3eh olh 3fh reserved vcc logic supply optimum write/erase voltage (highest performance) 50h (5.ov) v, progr amming supply optimum write/erase voltage (highest performance) 50h (5.ov) reserved for future versions of the scs spccitication rrrm-ot
sharp id246 series product overview 21 10. 2 sts configuration command the rdy/bsy# pin can be configured to different states using the sts configuration command. once the rdyi bsy# pin has been configured, it remains in that configuration until another configuration command is issued, the device is powered down or card is reset. upon initial power-up and after exit from deep power-down mode. the rdy/bsy# pin defaults to ry/by# operation where sts low indicates that the wsm is busy. sts high indicates that the wsm is ready for a new operation. to reconfigure the rdy/bsy# pin to other modes, the sts configuration is issued followed by the appropriate configuration code. the three alternate configurations are all pulse mode for use as a system interrupt. table 16. sts configuration coding description effects set sts pin to default level mode (ry/by#). ry/by# in the default level-mode of operation will indicate wsm status condifion. set sts pin to plused output signal for specific erase operation. in this mode, sts provides low pulse at the completion of block erase,full chip erase and clear block lock-bit ooeration. set sts pin to pulsed output signal for a specific write operation. in this mode, sts provides low pulse at the completion of (multi) byte write and set block lock-bit operation. set sts pin to pulsed output signal for specific write and erase operation.sts provides low pulse at the completion of block erase, full chip erase, (multi) word/byte configuration operations. t1158e-01 table 17. write protection alternatives operation block blken bit of write lock-bit protection resister effect block erase, i l i 0 1 block erase and (multi) word/byte write (multi) word/byte write h enabled. 1 i 1 block is locked. block erase and (multi) i word/byte write disabled. full chip erase set block lock-bit clear block lock-bits cl1 x x x block lock-bit override. block erase and (multi) word/byte write enabled. all unlocked blocks are erased, lockd blocks are not erased. all block lock-bit disabled. set block lock-bit disabled. set block lock-bit enabled. clear block lock-bit disabled. clear block lock-bit enabled. t1159e01
sharp id246 series product overview 22 11. electrical specifications 11. 1 absolute maximum ratings parameter r supply voltage 1 program voltage ~ input voltage operating temperature 1 storage temperature 1 note symbol rating unit 2 v v cc -0.3 to 6.0 2 v pp -0.2 to 7.0 v 2 vm -0.3 to vcc+0.3(max:6.0) v 1 t opfc 0 to 60 ?c tstg -20 to 65 ?c t1165e41 notes: 1. operating temperature is for commercial product defined by this specification. 2. all specified voltages are with respect to gnd. during transitions, this level may undershoot to -2.0~ for periods c20ns or overshoot to vcc+2.ov for periods <20ns. 11.2 recommended operating coriditions t1177e-01 11. 3 capacitance parameter input capacitance input/output capacitance ta=25 ?c , f= 1 mhz symbol min typ max unit condition gin - 15 - pf v,,=o.ov 50 - 25 - pf vo,=o.ov 11.4 ac input/output test conditions figure 5. transient input/output reference waveform figure 5 shows input/output level and test level for ac test. input rise and fall times (10% to 90%) < ions.
id246 series product overview 23 12. dc characteristics (ta=oto6o?c) parameter test condition output high voltage vcc read current (continue to next page) t1166e.01
sharp id246 serles product overview 24 dc characteristics (continued) (ta = 0 to 60c) v, stand-by or read v, deep power-down current v,, word write or set lock-bit current v,, block erase or clear lock-bit current v, word write or block erase suspend current v,, lockout voltage note: sym- bol i ppws 4pes v -el!5 test condition 40mb 520 520 ,ua v&vcc 48mb 5.50 550 6 ,u a 32mb 1.6 ma 40mb 2.0 ma v+vcc 48mb 2.4 ma 78 1.5 1.5 v tl lc7e-01 1. these parameters are applied to all input pins and all input/output pins in input mode. 2. these parameters are applied to ao-& and d,-dn in input mode and reset. 3. these parameters are applied to ce,#,ce,#,wb#,oe# and reg#. 4. these parameters are applied to rdy/bsy#. 5. these parameters are applied to d,-drs in output mode. 6. all currents are in rms unless otherwise notes. 7. block erase, word/byte write, and lock-bit configurations are inhibited when v,s v,,, and guaranteed in the v, voltage is vpp, , or v,. 8. sampled. cps0008e-00
sharp id246 series product overview 25 13. ac characteristics testing conditions : 1) input pulse level 2) input rise/fall time 3) input/output timing reference level 4) output load (including scope and jig capacitance) 1.5 to 3.5v (@vcc=5vk5%,vcc=5v~lo%) 0 to 3.ov (@vcc=3.3koo.3v) 1ons 2.5v (@vcc=5v+5%,vcc=5v+1oq) 1.5v (@vcc=3.3v&.3v) i-i-l-l,+loopf ( @vcc=~v+~%,vcc=~v~io%) il-i-l+sopf (@vcc=3.3v+o.3v) 13. 1 common memory read operations (ta = 0 to 60c) , ---- -bol vcc=3.3v+ 0.3v vcc=svk 5% 1 vcc=sv + 10% [jnit *:time until output becomes floating. (the output voltage is not defined.) ns tlc43-01
sharp id246 series product overview tfl 1 * address t(a) w e * b(a) w ce#, ce2# \ / / //// 4 to3 oe# dout figure 6. ac waveforms for read operations note) 1. we# = ?high?, during a read cycle. 2. either ?high? or ?low? in diagonal areas. 3. the output data becomes valid when last interval, ta (a), ta (ce) or ta (oe) have concluded.
sharp id246 series product overview 27 13.2 command write operations : common memory 13. 2. 1 we# controlled write operations parameter write cycle time address setup time write recovery time data setup time for we# data hold time oe# hold time from we# ce# setup time for we# address setup time for we# write pulse width we# high to rdy/bsy# going low reset recovery time v, setun time v, hold time word/byte write time block erase time set lock-bit time clear block lock-bits time word/byte suspend latency time to read erase suspend latency tie to read (vcc=3.3v rtd.3\ i, ta=o to 60c) symbol vcc=3.3v -tn ?v .?.a v ieee 1 pcmcia condition unit min i max i t t *?a-j rw i 250 ns 30 ns fwhq?4 v,,=3.3vko.3% v,,=5v+lo% 10.0 s v,,=3.3v~.3% 10.0 ps $ihrhi v,,=w *lo% 9.3 /is vpp=3.3vti.3% 21.1 ps v,*=5v *lo% 17.2 p?s t1168e-01
sharp id246 series product overview (vcc=svfi%, vcc=5v+lo%,, ta = 0 t parameter oe# hold time from clear block lock-bits erase suspend latency tie to read 60c ) ~ unit ~ ns 1 ns ns ns ns ns ns ns ns ns p?s ns ns ps s ps s 1169e-01 cpscw~e~io
sharp id246 series product overview data rdy/bsy# reset vu - t 1 i \ u i th(oe-w-l!) wkl vu whqvlz.3.4 3 viii , i- vu vu wtirhi.2 voh i e / -4 i vu h i i vw12 vpp vu 1. v,. power-up and standby 2. write data write or erase setup command 3. write valid address and data or erase comfirm command 4. automated data write or erase delay 5. read status register data 6. wrtte read array command fioic-03 figure 7. ac waveforms for write operations (we# controlled) note) while the data signal is in output mode, do not apply an opposite phase input signal.
sharp id246 series product overview 13. 2. 2 ce# controlled write operations (vcc=3,3v ti.3v, ta = 0 to 60c ) erase suspend latency tie t1170e-01
sharp id246 series product overview 31 parameter (vcc=sv y%, vcc=sv mo%, ta=o to 60c ) i??viibol ?yb vcc=sv y% vcc=sv +-lo% condition unit ieee --_ _--. kmcia i . i... . i. wr . . ..i i,.., write cycle time t a?.%? address setup time t write recovery time liz data setup time for ce# bveh data hold time &hdx oe# hold time from ce# acl write pulse width b.eh ce# high to rdy/bsy# _ going lo* hhrl w) i t (cm i 1 80 1 - 1 80 i - i ns i 1 - ( 140 1 - 1 140 1 ns 1 i clear block lock-bits time i i khqv.4 word/byte suspend latency time to read lrhl v,=w *lo% - 7.0 - 7.0 p s erase suspend latency tie to read v,,=5v *lo% - 13.1 - 13.1 #us t1171eql
sharp id246 series product overview 32 1. 2. 3. 4. 5. 6. address ain i viii tda)- b we# vil moe-c?3 4 viii oex vu hwe-ceh) i)- e lehqvi.23.4 hi 31#, cm vu. voh i tdyljsy# vol i i viii reset vll vppl.2 vpp vu 1. vcc power-up and standby 2. writr data write or erase setup command 3. write valid address and data or erase cohtflrh4 command 4. automated data wrlte or erase delay 5. read status register data 6. write read array command figure 8. ac waveforms for write operations (ce# controlled) note) while the data signal is in output mode, do not apply an opposite phase input signal.
sharp id246 series product overview 33 13. 3 attribute memory read operation (ta=o-60c) parameter read cycle time address access tie symbol vcc=3.3vf 0.3v vcc=sv az 10% unil ieee pcmcia min max mm max t avav tcr 600 - 300 - t *w-w l(a) - 600 - 300 ce# access time oe# access time output disable time from cel#,ce2# * output disable time from ce# output disable time from ce 1#,ce2# output disable time from oe# data valid tie from address change ~ tm.qv f glqv t ew2 t ghpz fn on7 i wm - 600 - 300 wei - 300 - 150 fdir(ce) - 150 - 100 moe) - 150 - 100 mm 5 - 5 - ns i t&9 ioi-iol-i 1 i i i i i i * : tie until becomes floating. (the output voltage is not defined) t1056-g note) when the cis constructed by eeprom, this card requires 5v voltage for vcc. address cel#, ce2# / i oe# / hiike) l&e) 4 i ta(oe) ) * ,.j tdis(oe) ._ dout high-inpedance data output is valid \\) /i/ figure 9. attribute memory read operation cpscwxe-001
sharp id246 series product overview 34 13. 4 attribute memory write operation (ta=o-60c) i address setup time ~ write recovery time 1 data setup time i data hold time /address setup time for we# 1 write pulse width setup time for oe# hold tie for oe# setup tie for ce# hold time for ce# symbol ieee 1 pcmcia vcc=3.3v f 0.3v vcc=5vt 1070 min 1 max min 1 max unit i i i i i i i t avav t cw 1 600 1 - 1 250 - ns llax l(we) 70 - 30 - ns t dvwh ?a@-weh) 150 - 80 - ns l uny k@) 70 - 30 - 150 - t1057.01 note) when the cis constructed by eeprom, this card requires 5v voltage for vcc. address cel#, ce2# oe# we# data f1057-01 figure 10. attribute memory write operation
sharp id246 series product overview 13.5 power-up/power down parameter ce# signal level (o.ov < vcc < 2.ov) ce# signal level (2.ov c vcc c vih) ce# signal level (vih c vcc) ce# setuo time reset setup time ce# recover time vcc rising time vcc falling time reset width reset width reset width symbol pcmcia notes / min / max / units / vi (ce) 1 0 vimax v 1 vcc-o. 1 vih4ax v 1 vu4 vih4ax v l? wcc) - 20 - ms tsu (reset) - 20 - ms notes: 1. vm~ means absolute maximum voltage for input in the period of o.ov < vcc < 2.0 v, vi (ce#) is only o.oov-v&fax 2. the tdr and tpf are defined as ?linear waveforms? in the period of 10% to 9010, or vice-versa. even if the tb (hi-z reset) - 1 - ms ts (hi-z reset) - 0 - ms waveform is not a ?liner waveform,? its rising and falling ime must meet this specification. -- tsu (reset) = -- t,, (hi-z reset) hi-z----------- 3e1# yz5jk-j ts (hi-z reset) -------------_ hi-z f1012-01 figure il. power-up/down timing i
sharp id246 series product overview 14. specification changes this datasheet is for id246 series product overview, and final specifications will be submitted for qualification of the memory card. please note that contents of this datasheet may be revised without announcement beforehand. please do not finalize a system design with this information. 15. other precautions . permanent damage occurs if the memory card is stressed beyond absolute maximum ratings. operation beyond the recommended operating conditions is not recommended and extended exposure beyond the recommended operating conditions may affect device reliability. . writing to the memory card can be prevented by switching on the write protect switch on the end of the memory card. . avoid allowing the memory card connectors to come in contact with metals and avoid touching the connec- tors, as the internal circuits can be-damaged by static electricity. + avoid storing in direct sunlight, high temperatures (do not place near heaters or radiators), high humidity and dusty areas. . avoid subjecting the memory card to strong physical abuse. dropping, bending, smashing or throwing the card can result in loss of function. . when the memory card is not being used, return it to its protective case. . do not allow the memory card to come in contact with fire.
sharp id246 series product overview - 0 a enlargement of the wr i te-protect sw itch i 16. external diagrams 935 t68 1. b,, - 50. 8 ii - . (substrate area) 1. 1 51. 8 i front ? c i 4 n a - 6ko.l onncc t area) \ 3. 3 f0. 1 w _i. i i \& 51. 8 \2-r2 cs"b?trotc area) back back cpswoge-00 protected 50. 8 1. 6 (fubrtrate area) (fubrtrate area) 1. 51 i- 41. 3 i i tiiickness tlaterial finish memory car0 name external diagram

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